Exemplary embodiments of the present invention relate to an integrated circuit, and more particularly, to a delay locked loop (DLL) of an integrated circuit.
In general, an integrated circuit such as a double data rate synchronous DRAM (DDR SDRAM) includes a delay locked loop (DLL) for allowing an internal clock signal and an external clock signal to have the same phase in order to compensate for time delay occurring in an internal circuit when using the external clock signal. In other words, the delay locked loop receives the external clock signal and compensates for a delay component of a clock path and a data path to reflect negative delay in advance, thereby allowing data outputted from the integrated circuit to be synchronized with the external clock signal.
Meanwhile, a clock signal may be distorted by noise and the like. In such a case, the duty cycle of the clock signal may be distorted. Then, the delay locked loop using such a clock signal is likely to perform an abnormal operation due to the clock signal with a distorted duty cycle, and the duty cycle of a clock signal outputted from the delay locked loop may also be distorted. In this regard, the semiconductor integrated circuit includes a duty correction circuit (DCC) in order to correct a change in the duty cycle of a clock signal, in addition to the delay locked loop.
FIG. 1 is a block diagram illustrating the configuration of a conventional integrated circuit.
Referring to FIG. 1, a conventional integrated circuit 100 includes an input buffer circuit 110, a delay locked loop 120, a duty correction circuit 130, and an output driver 140. The input buffer circuit 110 buffers an external clock signal EX_CLK inputted from the outside of the integrated circuit to output a reference clock signal REF_CLK. The delay locked loop 120 delays the reference clock signal REF_CLK by a delay time for delay locking to generate a delay locked clock signal DLL_CLK. The duty correction circuit 130 receives the delay locked clock signal DLL_CLK outputted from the delay locked loop 120 and performs a duty correction operation. The output driver 140 outputs inputted data DATA to a pad DQ in synchronization with an internal clock signal IN_CLK with a duty cycle corrected by the duty correction circuit 130.
Hereinafter, the operation of the integrated circuit 100 having the above configuration will be described.
The input buffer circuit 110 buffers the external clock signal EX_CLK to transfer a buffered signal to the delay locked loop 120 as the reference clock signal REF_CLK.
The delay locked loop 120 delays the reference clock signal REF_CLK by reflecting a delay time of a clock path and a data path of the integrated circuit, e.g., delay times occurring in the input buffer circuit 110 and the output driver 140, and outputs the delay locked clock signal DLL_CLK.
The duty correction circuit 130 adjusts a clock edge of the delay locked clock signal DLL_CLK outputted from the delay locked loop 120 and generates the internal clock signal IN_CLK with a constant duty cycle ratio of 50:50.
The output driver 140 outputs the inputted data DATA to the pad DQ in synchronization with the internal clock signal IN_CLK with the duty cycle corrected by the duty correction circuit 130.
The conventional integrated circuit 100 has the following features.
When the delay locked loop 120 is in an enabled state, the duty correction circuit 130 is also in an enabled state, continuously receives the delay locked clock signal DLL_CLK to perform the duty correction operation, and outputs the internal clock signal IN_CLK with a corrected duty cycle, since the external clock signal EX_CLK is continuously inputted. However, since the internal clock signal IN_CLK is used only for a specific operation such as a read operation, the conventional integrated circuit 100 may use a large amount of current.